The present invention relates generally to microelectronic dies, semiconductor chips or the like, and more particularly to a microelectronic die including a low resistive/capacitive (RC) under-layer interconnect structure.
In semiconductor chips, microelectronic dies or the like, some components may need to be interconnected for the transmission of signals between the components or so that power from a single source can be routed to the different components. These interconnected components are sometimes formed at different locations on the chip or die and can be at extreme distances across the die from one another because of design constraints. As the distance between interconnected components becomes longer, the more desirable that the conductive interconnect be denser or of a material to provide a lower resistance/capacitance (RC) interconnect for efficient and proper operation of the components. There is a tradeoff between providing denser, lower RC interconnects between components and the size of the microelectronic die or chip. Current structures providing additional low RC interconnects between components have necessitated that the dies or chips be made larger. However, the trend is to pack more components per square area on a die, to more efficiently utilize the available area on a die and to actually reduce the size of the die. Providing additional low RC interconnects between components can also result in several additional process steps that increase the time and expense of manufacturing the chip.
Accordingly, for the reasons stated above, and for other reasons that will become apparent upon reading and understanding the present specification, there is a need for low RC interconnects that efficiently utilize the available area on a microelectronic die without requiring additional area or requiring that the die be made bigger. Additionally, there is a need for a method of forming low RC interconnects that require a minimum of additional process steps and therefore minimize the additional time and expense of forming the low RC interconnects.
The above mentioned problems with forming low RC interconnects are addressed by the present invention and will be understood by reading and studying the following specification. Low RC interconnects, memory cells and systems are provided by the present invention that efficiently utilize the existing available area on a die and do not require that the die be made bigger. Methods of fabricating low RC interconnects, memory devices and systems are also provided by the present invention that require minimal additional processing and actually form the low RC interconnects utilizing some of the same operations used to form other components.
In accordance with the present invention, a microelectronic die includes a first area, a second area and an under-layer of conductive material formed in the second area to interconnect components.
In accordance with an embodiment of the present invention, a microelectronic die includes a first area and a second area. An elongated trench is formed in the second area and extends substantially across the microelectronic die. A line of metallization is formed in the elongated trench to transmit signals between different components or across the microelectronic die.
In accordance with another embodiment of the present invention an electronic system includes a processor and a memory system coupled to the processor. The memory system includes a layer of insulative material and an array of memory cells formed in a first area of the layer of insulative material. At least one trench is formed in a second area of the layer of insulative material. A plurality of components is formed in a third area of the layer of insulative material and at least one line of metallization formed in the at least one trench to transmit signals between the plurality of components.
In accordance with another embodiment of the present invention, a method of making a microelectronic die includes forming a layer of insulative material on a substrate; forming at least one trench in the layer of insulative material extending from proximate one edge of the microelectronic die to proximate another edge of the microelectronic die; and forming at least one line of conductive material in each of the at least one trenches to transmit signals across the microelectronic die.